Overview

The R8051XC2 configurable processor core implements a range of fast, 8-bit, microcontrollers that execute the MCS®51 instruction set.  

The IP core runs with a single clock per machine cycle, and requires an average of 2.12  machine cycles per instruction. Dhrystone 2.1 tests show it to run from 9.4 to 12.1 times  faster than the original 8051 at the same frequency. Representative 90 nm ASIC results  have reached 430 MHz, for an effective speed-up of 400 times over 80C51 chips. 

The core has a rich set of optional features and peripherals. Designers can choose from  several versions, including the easy-to-configure full version with all options included; a  custom, non-configurable version with options specified at purchase; and pre-packaged  versions with different sets of options and degrees of configurability. 

All versions of the core benefit from power-saving architectural efficiency—the  R8051XC2 is 10% better in milliwats/DMIP than our previous generation—and various  power-management options are available. System development is facilitated through a native on-chip debugging option and support by development tools from Keil and IAR.  

This product builds on our rich experience with hundreds of 8051 IP customers going  back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core  is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI  modules), synchronous reset, and no internal tri-states. Representative 90nm ASIC results show the core to be conservative in its use of space, requiring just 8,000 to 71,000  gates.