A leading IP provider for electronic system designers

USB IP

WWAGO's USB  IP cores are excellent IP cores, we can provide both USB Controller core and USB PHY. 
              USB2.0 Device  controller core
              USB2.0 OTG  controller core
              USB3.0 SuperSpeed Device controller Core
              USB3.0 SuperSpeed Host controller Core
              USB3.0 SuperSpeed OTG  Core
              Wireless USB controller  Core
              Ultra Wide Band (USB) MAC controlle Core        
              USB2.0 PHY     
              USB3.0 PHY  
our controller IP cores are available in synthesizable RTL source code for ASICs, or optimized netlists for FPGAs and Structured ASICs. Our licensing is simple and flexible to match engineers’ needs.

our USB2.0 PHY and USB3.0 PHY currently are available on TSMC technology nodes.and our standard deliverables are as below:
              *    PCS RTL: Compliant soft-IP with design constraints for physical implementation
              *    SerDes PMA behavioral model along with test benches for verification
              *     LEF abstracts for physical implementation
              *     Liberty Timing Views (.lib) for multi-corner timing analysis
              *     GDSII with DFM for high manufacturability
              *     DFT Models: Scan models for the hard-macro for ATE vector generation
              *     Documentation: Data Sheets, PCS MAS, RTL Application Notes, SerDes Layout Integration Guidelines, 
                     Package/Board  guidelines, Test Plan, DFT Specifications

For more information, please call us  by call or  by mail: sales@wwago-inc.com